半導体製造ラボ

公式求人詳細

Senior Program Managers

インテルの公式求人。勤務地は東京都、採用区分は中途、職種カテゴリはコーポレートです。

分類・ページ生成
2026/07/27
求人DB生成
2026/07/25

応募判断に必要な情報を先に確認

必須・歓迎・働き方

公式求人票の明記内容のみ

必須 応募条件

  • Minimum qualifications are required to be initially considered for this position.
  • Bachelor's or Master's degree with 8+ years, or PhD with 4+ years work experience, in Science or Engineering.6+ years of experience in fab back-end or substrate manufacturing process develo…

歓迎 あると活かせる経験

  • qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
  • Experience in capacity management, lead time analysis, yield improvement, structured problem solving, situational leadership, supplier influence, and stakeholder management.Strong understan…

働き方 勤務条件

勤務地
東京都
リモート
記載なし
勤務帯
記載なし
出張
出張多め・定期出張
オンコール
記載なし
転居
記載なし
想定役割
管理職・マネージャー
転勤
記載なし

公式募集要項で最新条件を確認

求人市場で見るこのポジション

企業・同職種・必須スキルの比較

求人市場分析を見る

企業 × 関連工程

同社の公開求人全体

純増減 +5件

当DBの直近90日観測で、インテルは新規 5件・終了 0件。現在公開 5件です。

同職種の掲載給与

プロジェクト / プログラム管理

中央値 1,395万円

掲載年収レンジの中点を比較。給与確認済み 4件/同職種 15件です。

類似求人の必須スキル

プロジェクト / プログラム管理

  • 業務英語 6件 40%

新規・終了は当DBでの観測差分であり、市場成長や採用需要の増減を単独では示しません。 直近30日は収集対象拡張の影響を含みます。

企業公式情報から整理

募集要項

企業の公式採用ページまたは公式に委任された採用システムの公開情報を、項目別に整理しています。 確認できない条件は推測せず、公式募集要項への案内を表示します。

3/8 公式情報で確認できた項目

仕事内容

公式情報あり

Job Description

The Advanced Packaging Technology Development Substrate and Wafer Assembly (APTD: S and WA) team develops and delivers advanced substrate packaging and wafer assembly solutions for customers. As part of the Substrate Technology Integration Group, within APTD, you will play a pivotal role in shaping the future of advanced packaging. In this role, you will:Work at the forefront of packaging technologies essential for next-generation AI devices.Collaborate with substrate suppliers worldwide to drive innovation and scalability.Contribute to the deployment of EMIB-T, our next-generation advanced packaging substrate technology, enabling heterogeneous chip architectures.Lead efforts to qualify new capacity at advanced packaging suppliers, ensuring timely readiness to meet growing customer demand. We are seeking highly motivated professionals with strong technical expertise who thrive on solving complex challenges, challenge conventional approaches, and build lasting supplier partnerships. Note: This position requires regular onsite presence to fulfil essential responsibilities.Key Responsibilities:Collaborate closely with on-site supplier engineering teams and the US integration team to advance substrate building block technologies and manage critical process interactions.Monitor, optimize, and improve capacity in bottleneck processes by implementing strategies that reduce throughput time (TPT).Oversee schedules for product and test vehicle (TV) deliveries, proactively resolving issues to achieve aggressive on-time delivery (OTD) targets.Conduct thorough analysis of substrate lead times, develop reduction roadmaps, and consistently meet quarterly lead time goals.Ensure strict adherence to Process Control System (PCS) commitments by suppliers.Partner with internal teams to design and execute new factory TV/product certification plans focused on yield improvement.Develop and maintain detailed micro-schedules for new factory startups, including milestone tracking to ensure supplier compliance with startup timelines.Lead qualification activities and monitor ramp indicators to guarantee smooth, incident-free production ramp-up of new capacity.Influence strategic decision-making at senior supplier management levels. Work Environment:Regular travel to supplier sites and onsite presence at factories (minimum three days per week).Collaboration with diverse teams across Asia and the US.Flexibility to adapt to evolving project scopes and dynamic business needs.Qualifications:Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications: Bachelor's or Master's degree with 8+ years, or PhD with 4+ years work experience, in Science or Engineering.6+ years of experience in fab back-end or substrate manufacturing process development. Preferred Qualifications: Experience in capacity management, lead time analysis, yield improvement, structured problem solving, situational leadership, supplier influence, and stakeholder management.Strong understanding of substrate process building blocks such as component embedding, laser drilling, dielectric lamination, lithography, multi-metal electrolytic plating, defect inspection/metrology, and electrical testing.Experience qualifying /owning process tools in a TD/ramp or HVM context is desired. Hands-on experience in factory operations, substrates, manufacturing, process engineering, and yield improvement is highly preferred.Fluent business-level English communication skills, excellent presentation abilities, and capability to engage effectively with supplier executive management. Job Type:Experienced HireShift:Shift 1 (Japan)Primary Location: Japan, TokyoAdditional Locations:Business group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/AWork Model for this RoleThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

対象となる方

公式ページで確認

当サイトが取得した公式公開情報では確認できません。応募前に最新の公式募集要項をご確認ください。

勤務時間

公式ページで確認

当サイトが取得した公式公開情報では確認できません。応募前に最新の公式募集要項をご確認ください。

給与

公式ページで確認

当サイトが取得した公式公開情報では確認できません。応募前に最新の公式募集要項をご確認ください。

待遇・福利厚生

公式ページで確認

当サイトが取得した公式公開情報では確認できません。応募前に最新の公式募集要項をご確認ください。

休日・休暇

公式ページで確認

当サイトが取得した公式公開情報では確認できません。応募前に最新の公式募集要項をご確認ください。

求人情報

求人名
Senior Program Managers
会社名
インテル
半導体直接関連度
B:半導体事業支援職
職種カテゴリ
コーポレート
勤務地
東京都
都道府県
東京都
地域区分
関東
公式記載の勤務地
東京都
勤務地確認
通常
採用区分
中途
雇用形態
正社員
給与
公式募集要項で確認
求人取得日
2026/07/21
最終監査日
2026/07/21
掲載状態
募集中
公式募集要項
掲載元を開く
公式応募ページ
応募ページを開く

5軸分類

企業カテゴリ
半導体デバイス
職種ファミリー
コーポレート
具体職種
プロジェクト / プログラム管理
対象製品
半導体パッケージ
関連工程・技術
工程未分類
半導体直接関連度
B:半導体事業支援職
関連職種
コーポレート / プロジェクト / プログラム管理
関連工程
工程未分類
関連技術
未分類
勤務地エリア
関東

一部分類項目は未確認です。公式募集要項と確認根拠を併せて確認してください。

半導体直接関連度の判定根拠

B:半導体事業支援職 — 半導体事業・工場・顧客を、営業・調達・施設・IT・法務などから支える仕事

判定の確度:B(半導体事業を支援する業務)

The Advanced Packaging Technology Development Substrate and Wafer Assembly (APTD: S and WA) team develops and delivers advanced substrate packaging and wafer assembly solutions for customers. As part of the Substrate Te…

類似求人